Hello All,
I have a design using an SPI slave (PSoC 3/5) with the following parameters:
- CPHA=0, CPOL=1
- MSB First
- No data being received (MOSI is zero constant)
- 8-bits wide
- 4 Byte FIFO
- External Clock (24 MHz BUS_CLK)
The application requires that, while SCLK is in its idle state, MISO be a steady high to indicate that the device is ready for a data transfer. Immediately after the last SCLK, the MISO must go low to indicate that the device is not yet ready for another transfer. Once the device is ready, the MISO will go high. I can add logic to the SPIS to force these conditions, but before I do that, I think I should better understand the SPI slave.
I will only transfer 4 bytes at a time. And, since the clock is much faster than SCLK, I consider a delay of a few clock cycles to be essentially instantaneous. I don't want to use the SS input, but if I have to, I'll use internal signals to "fake it out". That being said, I want to determine/control the MISO state before and after the transfer.
Assume that the FIFO is full and I have written directly to the shift register using SPIS_WriteTxData() before the first leading (falling) SCLK edge. What is the MISO state? Is it equal to the MSb of the first byte, already in the shift register?
Also, what would the MISO state be after the trailing (rising) edge of SCLK? Would it be the LSb of the final byte, the MSb of the next byte from the FIFO, or something else?
Any help would be appreciated.
Paul
