Hello everyone,
I'm new to this controller and I'd be happy to get some help with how to start programming.
My goal is to build a card that can receive electrical voltage and convert it to me for information I can transfer to the computer.
I need a total of 10 I / O ports plus 2 digital.
I'd be happy for help with code or guidance on how to start setting things up what i need to difine as input as voltage and how to create output as binary data

Thanks 

matan

I have read through all the DMA notes and USB datasheet and I am just a little confused conceptually on the best way to steam ADC data over USB. I am using the EOC on a Sequencing ADC to trigger a DMA channel from the final array of the ADC to the a ping pong buffer, and I would like to stream the data over USB. Using DMA with manual buffer management this is pretty straightforward: Each TD triggers an interrupt and the ISR sends the inactive (full) buffer to the USB using loadInEP().

I was thinking it would be better to use USB DMA with automatic buffer management since it would enable the use of a larger buffer for each loadEP (it is an ISO endpoint), but since the source array changes each time I need to call load it seems like I would have to call loadEP twice? the first time sets the new source array and the second time triggers the DMA? this is more complicated than the manual DMA it seems for this kind of setup.

If I set up DMA directly from the ADC results buffer (two bytes, since I am sequencing two channels at 8-bits each) to the USB ISO endpoint would it buffer them and send a full packet at once or would it just send a ton of two-byte packets?

Does anyone know if there is a way to determine a component's version number at compile time (or run time)?  I want to do this is because there is an error with the SPI Slave current version (2.70).  The Tx FIFO Empty line doesn't clear properly.  This error is listed in the errata section of the datasheet and is slated to be fixed in the future.  Until then, I have a workaround.  However, once the error is fixed, the workaround would cause problems.

I thought that, if there were a way to read the component's version number, I could conditionally compile the workaround.  However, the only place in the component's header file that had a version number was a comment line.  I have searched through various project/system header files, but found no component version numbers.

Any suggestions would be appreciated.

Paul

I am making a basic "oscilloscope" project using the PSOC-5 and I thought I had it all working smoothly till I wrote the PC software to visualize the data. I am using a SAR_SEQ ADC with two channels. The EOC output of the ADC goes into a demux that feeds four different DMA channels, each with its own TD, buffer, and interrupt. This is to implement a hardware-based ping pong buffer, and the interrupt output of each DMA is routed not only to and ISR (that loads the now full buffer into the IN endpoint) but also to a counter that will move the EOC signal to the next DMA channel. In case I am not explaining this well I have attached a picture of that schematic page.

The problem is this: The buffers are 500 bytes, and since each result from the ADC is an array of two 16 bit numbers, the first byte should be the same channel in every packet, and the second byte should be the other channel. But as data is streamed the order changes randomly. I know ISOC transfers can loose data but none of the packets are marked as bad and all packets received are full sized.

Troubleshooting steps:

• Added more DMA channels to the buffer cycle (it was only two originally)
• Used wireshark to sniff USB traffic over usbmon to eliminate the possibility of stupid mistakes in my PC app.
• Slowed down the clock triggering the ADC to 100kHz
• Made buffers on PSOC smaller (still even size of course) to not "stress" the usb bus.

I am kind of at a loss, not sure what to do or test at this point. I am new to USB but thought the PSOC was a great place to start with the great documentation and examples. I attached the project as well in case anyone is interested.

I'd like to use OOP practices for my application code. Does PSoC Creator allow this or is there a way to integrate with external environment/tools? Please advise where to look. Thank you.

I'm trying to detect a UART data that uses a mark/space as parity bit,
I tried the following code but it doesn't seem to work for me.

temp = UART_GetChar()
if(temp != 0)
{
If(UART_ReadRxStatus() & UART_RX_STS_MARKSPS)
{
while(USB_CDCIsReady() == 0);
USB_PutChar('M')
}
else
{
while(USB_CDCIsReady() == 0);
USB_PutChar('S')
}
}

The usb always returns an S regardless of the parity bit and the data that is being received.
The data is being received correctly though I just can't detect whether the parity bit is high or low.

Is there an API to stall an endpoint? Nothing obvious in the code or documentation.

TAIA.

All,

I am having some trouble using the SPI Slave UDB in my latest project. We are using two PSoC 5LP devices to communicate with one another via SPI. Both of the SPI Blocks are on mode (2 I believe, CPHA =1 CPOL = 0). I have verified that the data that I am attempting to send is correct on my oscilloscope, but my SPI slave block is not reading/interpreting this data correctly. It will sometimes work correctly and the data is correct, but most if not always the data is shifted by bit and that disrupts my message formatting.

I have attached the screenshot from the oscilloscope to this forum post as well as a recent and working copy of the project.

1- SCLK

2- MISO

3- MOSI

4- SS

The messages that are intending to be sent are: 0xAA 'S''3' 0x55 0x55 0x55 0x55 0x55 0x00

0xAA 'P''B''?' 0x55 0x55 0x55 0x55 0x00 0x00

Please let me know if there is anything you recommend me to do.

Hi ,

I am having problems with unpredictable DMA transfers. sometimes everything works, sometimes it seems that the DMA is either not working at all or running over data structures in memory.  

I have a SPI-Slave connected to 2 different DMA components. each responsible for copying data from the SPIS to a different buffer. 
the idea is to switch the active DMA between the two allowing time to handle the data in the other buffer without losing data. since the packet size is dynamic, a mechanism is in place to get the position of the DMA destination address so a packet size could be calculated.

setting the DMA is using (example for one of the channels):

channel_rx_1 = DMA_Rx_1_DmaInitialize(1,1, HI16((uint32)SPIS_RXDATA_PTR), HI16((uint32)(slaveRxDataBuffer_1) );
TD_rx_1= CyDmaTdAllocate();
CyDmaTdSetAddress(TD_rx_1, LO16(((uint32)SPIS_RXDATA_PTR)), LO16(((uint32)slaveRxDataBuffer_1));
CyDmaTdSetConfiguration(TD_rx_1,MAX_BUFFER_SIZE, 0xFF,TD_INC_DST_ADR);
CyDmaChSetInitialTd(channel_rx_1, TD_rx_1);
CyDmaChEnable(channel_rx_1, 0)

stopping (when packet is over) using :

CyDmaTdGetConfiguration(TD_rx_1,&dma_location,0,0); //get size of packet
CyDmaChDisable(channel_rx_1);
CyDmaChFree(channel_rx_1);
CyDmaTdFree(TD_rx_1);

this repeats (enabling and disabling) every time a packet is received. jumping from DMA A to DMA B as the active one.
only the drq on the active one will be triggered.

is this the best way to jump between 2 DMA channels ? is there something wrong with the setup/stopping of the DMA ?  

Hi,
We are trying to acheive something like Sigma-Delta ADC -> DMA -> Filter_Block -> DMA -> SRAM. Initially we started testing
with ADC -> DMA -> Filter_Block-> Interrupt. The readings obtained were as expected. However when we tried replacing the 
interrupt with DMA {Sigma-Delta ADC -> DMA -> Filter_Block -> DMA -> SRAM} we noticed the readings not as expected. 
For the 50 tap filter the readings kept changing till the 49th sample and then it remained constant. 
I have attached the project bundle. Kindly help me figure out the issue ?

Thanks

Hello. I am using the delta sigma ADC in PSOC5. I am using a 12-bit resolution, and calls ADC_DelSig_Read16() when i want to recieve a value from the ADC. 

My problem is that i am unaware of how the 12-bit value is stored in a 16-bit variable.

Lets say that i got a value of 0xABC from my ADC. How will it be stored?

0x0ABC

0xABC0

Or in a whole different way?

What is the best method to access the USB CDC buffer in real time?  It has been no problem at all transmitting packets around 1kB, however, the API accessors seem to only update upon the completion of a full packet.

The USB CDC output is limited by memory, whereas the CDC input buffer is limited to 64kB.

I have source code to attach for reference if needed.

I also understand that this task is best suited for isochronous transfer, but there is an old driver used on the host side that is necessary.

Hi,

i have a problem with DMA. I split the DelSig ADC with a logic into two channels; A &B. That seems to work quite well. But the data I transfer with DMA doesn't look good. I am not sure if I need to use CY_DMA_TD_INC_SRC_ADR | CY_DMA_TD_INC_DST_ADR or not. If I use above configuration parameter for both channels, the values are static in the array (even if I feed the ADC with a sinus-signal). If I just write 0 configuration for both channels, the values seems to me nonsense and quite noisy even if the input voltage is stable.

After that DMA transfer I have some further transfers to feed values into DFB-Filter block.

An example for my code which is the same for channel B, is attached code example.

The goal of the logic with DMA transfer is to toggle between channel A and B. When 10 samples are full, I immediately transfer that SRAM -array to the next task with another DMA.

I hope someone can help.

BR

Rob

I'd like to make DMA transfer 2 data from SAR ADC to Memory as switching AmuxHW, but the output of DAC was mixed signal of 2 data (reference to attached picture:Blue= SIG1, Yellow=SIG2, Green=output of DAC). 

Digital delay circuit was referenced to CE95299 (http://www.cypress.com/documentation/code-examples/ce95299-delta-sigma-a...). 

I'm programming a CY8CKIT-010 using SWD and 5V from a miniProg3. The board has a 32.768 kHz xtal onboard.

After programming, the RTC is no longer running, but no changes were made to clock settings, etc. This happened intermittently with different boards, usually only while the programmer was plugged in, but now the clock doesn't appear to run on some boards while it does on others.

All boards are running the same program. I occasionally had external power on the board simultaneously with the programmer's supplied 5V.

I suspected the 32khz xtal signal and verified it with an osilloscope. The boards that are consistently not working appear to have a more rounded clock signal, but I haven't compared side by side to verify.

All this makes me think I did some damage to the board.

Any suggestions?

I have a FreeSoc2 development board with the 5888 part, MASTER_CLOCK comes from an external 24MHz crystal and is bumped up to 64MHz by the PLL. BUS_CLK==MASTER_CLK. Release build with LTO etc. enabled, optimization goal set to speed. Debugging a soft 3-wire SPI implementation I ended up with the following snippet:

    for(;;) {
    
        Soft_SCLK_DR |= (1 << Soft_SCLK_SHIFT);
        Soft_SCLK_DR &= ~(1 << Soft_SCLK_SHIFT);
    }

The output frequency on the Soft_SCLK pin is 4MHz -- I expected it to be in the 15-20MHz ballpark. So why is it so slow?

I've been tearing my hair out trying to figure this one out for hours and hours and hours.

I have a HID bootloader.  It has a light, and a button to force enable it.  It works.  I also have HID firmware that works.

I'm trying to have software switch from the active firmware to the bootloader.  I call Bootloadable_Load, and the light flickers for a second, but it won't stay in the bootloader, and jumps back to the application immediately.

I've tried stopping and restarting USBFS on the bootloader, on the bootloadable application.  I've paused after calling stop, removed the start() commands from the bootloader (so it would match one of the cypress examples).  I've added delay loops in to try to delay starting the bootloader - it's acting almost like Bootloadable_Load is running the bootloader component directly, rather than the bootloadable firmware.

I've tried having the ISR set a global flag instead of directly jumping.

At this point, I don't know what could be causing the problem.  I've set my ISR to just call Bootloadable_Load every 10 seconds - the LED blinks for a very short time from the bootloader, then it goes right back into the main firmware.

The code is on GitHub (in the GHETT-IO folder, and Bootloader folder).  If anyone has experience with something like this, or ideas why it would happen, I'd be rather appreciative.

https://github.com/kategray/technomotion-io/tree/bootloader
https://github.com/kategray/technomotion-io/archive/bootloader.zip

Hi everyone!

I'm trying to use the MiniProg3 for CSD Tuning. I have found two posts on this, but none helped.

I'm using the 014008 PSoC BLE.

When using the EvalBoard on the Pioneer Kit, and going to CSD Tuning from PSoC Creator, everything works as planned.

Now if using the MiniProg3 on the EvalBoard, I can program the PSoC through PSoC Programmer, but I can't get CSD Tuning to work.

The CapSense Tuner App will find the MiniProg, open the bridge correctly, but when trying to retrieve data, it will get a very stable "there was a problem reading data from the device" error.

The project within the PSoC is the simplest possible: just one CapSense and EZI2C, CapSense scanning within the loop. It's directly following the Application Notes. Debug is not using SWD but GPIO in order CSD Tuner not to be troubled by Debug.

I have tried many settings on the EZI2C (frequency, address, addressing method), different voltage, used the 5p and 10p connectors, used other EvalBoard, tried on a custom PCB (so outside the EvalBoard), used the Bridge Control Panel to ensure I2C was correctly configured ... still blocked.

Edit: could it be the fact the EZI2C block cannot "reach" the P0_6 and P0_7 Debug pins of the 014008 used by the MiniProg?

Any idea?

Hello All,

I'm trying to transfer a few values between an array and a datapath register and FIFO.  However, I don't have a good grasp on the ins and outs of DMA.  I think I've figured it out, but I was wondering if anyone could give my work a glance.

I have the following:

1. A 16-bit datapath whose instance name is DelHist_SM_DP
2. An array defined as uint16 DelHist_I_target [5]
3. A DMA whose instance name is DelHist_Target_DMA

When the drq line on the DMA is pulsed, I want the following to occur:

1. Transfer first value (2 bytes) in the array to the datapath data register D0.
2. Fill the datapath FIFO F0 with the remaining 4 values (8 bytes total) of the array.

Since I don't understand the DMA very well, I relied on the DMA wizard to set it up.  I have attached a screenshot of my entry.  The output of the wizard (with one modification) is below.  Note that, because the wizard didn't recognize the datapath, I had to tell it that I was doing an SRAM to SRAM transfer, then manually modify the destination base.

Am I on the right track?

Paul

/* Defines for DelHist_Target_DMA */
#define DelHist_Target_DMA_BYTES_PER_BURST 127
#define DelHist_Target_DMA_REQUEST_PER_BURST 0
#define DelHist_Target_DMA_SRC_BASE (CYDEV_SRAM_BASE)
// #define DelHist_Target_DMA_DST_BASE (CYDEV_SRAM_BASE)
#define DelHist_Target_DMA_DST_BASE (CYDEV_PERIPH_BASE)        // Modified base address

/* Variable declarations for DelHist_Target_DMA */
/* Move these variable declarations to the top of the function */
uint8 DelHist_Target_DMA_Chan;
uint8 DelHist_Target_DMA_TD[2];

/* DMA Configuration for DelHist_Target_DMA */
DelHist_Target_DMA_Chan = DelHist_Target_DMA_DmaInitialize(DelHist_Target_DMA_BYTES_PER_BURST, DelHist_Target_DMA_REQUEST_PER_BURST,
    HI16(DelHist_Target_DMA_SRC_BASE), HI16(DelHist_Target_DMA_DST_BASE));
DelHist_Target_DMA_TD[0] = CyDmaTdAllocate();
DelHist_Target_DMA_TD[1] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DelHist_Target_DMA_TD[0], 2, DelHist_Target_DMA_TD[1], TD_AUTO_EXEC_NEXT);
CyDmaTdSetConfiguration(DelHist_Target_DMA_TD[1], 8, CY_DMA_DISABLE_TD, DelHist_Target_DMA__TD_TERMOUT_EN);
CyDmaTdSetAddress(DelHist_Target_DMA_TD[0], LO16((uint32)DelHist_I_target), LO16((uint32)DelHist_SM_DP_D0_PTR));
CyDmaTdSetAddress(DelHist_Target_DMA_TD[1], LO16((uint32)&DelHist_I_target[1]), LO16((uint32)DelHist_SM_DP_F0_PTR));
CyDmaChSetInitialTd(DelHist_Target_DMA_Chan, DelHist_Target_DMA_TD[0]);
CyDmaChEnable(DelHist_Target_DMA_Chan, 1);

I have a CY8C5868AXI-LP032 application where I transfer packets to the PC over a CDC USB interface. It works fine both with the standard API and when I enable CDC API and use that API. It works with Manual (Static Allocation) as well as DMA (Manual Buffer Management), both of these have identical performance numbers (~850us to transfer 128bytes where 10us is needed for the USBFS_LoadInEP(EP2, *txBuffer, length); to execute). When changing to DMA with Automatic Buffer Management, nothing works anymore. I have followed the setup I found in examples and the datasheet (http://www.cypress.com/file/139686/download) but I have not been able to find an example project with CDC using DMA. Any hints on what I am doing wrong? Also, calling USBFS_LoadInEP should not take long when using DMA, right?